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| 1 ltc2421/ltc2422 24212f 1-/2-channel 20-bit m power no latency ds tm adcs in msop-10 n weight scales n direct temperature measurement n gas analyzers n strain gauge transducers n instrumentation n data acquisition n industrial process control no latency ds is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation. pseudo differential bridge digitizer , ltc and lt are registered trademarks of linear technology corporation. the ltc ? 2421/ltc2422 are 1- and 2-channel 2.7v to 5.5v micropower 20-bit analog-to-digital converters with an integrated oscillator, 8ppm inl and 1.2ppm rms noise. these ultrasmall devices use delta-sigma technology and a new digital filter architecture that settles in a single cycle. this eliminates the latency found in conventional ds converters and simplifies multiplexed applications. through a single pin, the ltc2421/ltc2422 can be configured for better than 110db rejection at 50hz or 60hz 2%, or can be driven by an external oscillator for a user defined rejection frequency in the range 1hz to 120hz. the internal oscillator requires no external fre- quency setting components. these converters accept an external reference voltage from 0.1v to v cc . with an extended input conversion range of C12.5% v ref to 112.5% v ref (v ref = fs set C zs set ), the ltc2421/ltc2422 smoothly resolve the off- set and overrange problems of preceding sensors or signal conditioning circuits. the ltc2421/ltc2422 communicate through a 2- or 3-wire digital interface that is compatible with spi and microwire tm protocols. n 20-bit adcs in tiny msop-10 packages n 1- or 2-channel inputs n single supply 2.7v to 5.5v operation n low supply current (200 m a) and auto shutdown n automatic channel selection (ping-pong) (ltc2422) n no latency: digital filter settles in a single conversion cycle n 8ppm inl, no missing codes n 4ppm full-scale error n 0.5ppm offset n 1.2ppm noise n zero scale and full scale set for reference and ground sensing n internal oscillatorno external components required n 110db min, 50hz/60hz notch filter n reference input voltage: 0.1v to v cc n live zeroextended input range accommodates 12.5% overrange and underrange n pin compatible with ltc2401/ltc2402 analog input range zs set ?0.12v ref to fs set + 0.12v ref (v ref = fs set ? zs set ) v cc f o fs set zs set sck ch1 sdo gnd cs reference voltage zs set + 0.1v to v cc 0v to fs set ? 100mv ch0 = internal osc/50hz rejection = external clock source = internal osc/60hz rejection 3-wire spi interface 1 f 110 9 8 7 6 2 3 4 5 2.7v to 5.5v ltc2422 24212 ta01 v cc v cc fs set zs set sck ch0 sdo f o cs ch1 gnd ltc2422 3-wire spi interface internal oscillator 60hz rejection 1 9 2.7v to 5.5v 8 7 10 6 24012ta02 2 4 3 5 descriptio u features applicatio s u typical applicatio u
2 ltc2421/ltc2422 24212f order part number (notes 1, 2) supply voltage (v cc ) to gnd .......................C 0.3v to 7v analog input voltage to gnd ....... C 0.3v to (v cc + 0.3v) reference input voltage to gnd .. C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) t jmax = 125 c, q ja = 130 c/w LTC2421CMS ltc2421ims absolute m axi m u m ratings w ww u package/order i n for m atio n uu w 1 2 3 4 5 v cc fs set ch1 ch0 zs set 10 9 8 7 6 f o sck sdo cs gnd top view ms10 package 10-lead plastic msop operating temperature range ltc2421/ltc2422c ................................ 0 c to 70 c ltc2421/ltc2422i ............................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ms10 part marking ltc2422cms ltc2422ims ltuz ltva ms10 part marking ltux ltuy t jmax = 125 c, q ja = 130 c/w parameter conditions min typ max units resolution l 20 bits no missing codes resolution 0.1v fs set v cc , zs set = 0v (note 5) l 20 bits integral nonlinearity fs set = 2.5v, zs set = 0v (note 6) l 4 10 ppm of v ref fs set = 5v, zs set = 0v (note 6) l 8 20 ppm of v ref offset error 2.5v fs set v cc , zs set = 0v l 0.5 10 ppm of v ref offset error drift 2.5v fs set v cc , zs set = 0v 0.04 ppm of v ref / c full-scale error 2.5v fs set v cc , zs set = 0v l 4 10 ppm of v ref full-scale error drift 2.5v fs set v cc , zs set = 0v 0.04 ppm of v ref / c total unadjusted error fs set = 2.5v, zs set = 0v 8 ppm of v ref fs set = 5v, zs set = 0v 16 ppm of v ref output noise v in = 0v (note 13) 6 m v rms normal mode rejection 60hz 2% (note 7) l 110 130 db normal mode rejection 50hz 2% (note 8) l 110 130 db power supply rejection, dc fs set = 2.5v, zs set = 0v, v in = 0v 100 db power supply rejection, 60hz 2% fs set = 2.5v, zs set = 0v, v in = 0v, (notes 7, 15) 110 db power supply rejection, 50hz 2% fs set = 2.5v, zs set = 0v, v in = 0v, (notes 8, 15) 110 db the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v ref = fs set C zs set . (notes 3, 4) co n verter characteristics u 1 2 3 4 5 v cc fs set v in nc zs set 10 9 8 7 6 top view ms10 package 10-lead plastic msop f o sck sdo cs gnd consult factory for parts specified with wider operating temperature ranges. 3 ltc2421/ltc2422 24212f symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 9) l 2.5 v sck 2.7v v cc 3.3v (note 9) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 9) l 0.8 v sck 2.7v v cc 5.5v (note 9) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o i in digital input current 0v v in v cc (note 9) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 9) 10 pf sck v oh high level output voltage i o = C 800 m a l v cc C 0.5 v sdo v ol low level output voltage i o = 1.6ma l 0.4 v sdo v oh high level output voltage i o = C 800 m a (note 10) l v cc C 0.5 v sck v ol low level output voltage i o = 1.6ma (note 10) l 0.4 v sck i oz high-z output leakage l C10 10 m a sdo digital i puts a d digital outputs u u symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode cs = 0v (note 12) l 200 300 m a sleep mode cs = v cc (note 12) l 20 30 m a power require e ts w u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v in input voltage range (note 14) l zs set C 0.12v ref fs set + 0.12v ref v fs set full-scale set range l 0.1 + zs set v cc v zs set zero-scale set range l 0fs set C 0.1 v c s(in) input sampling capacitance 1 pf c s(ref) reference sampling capacitance 1.5 pf i in(leak) input leakage current cs = v cc l C100 1 100 na i ref(leak) reference leakage current v ref = 2.5v, cs = v cc l C 100 1 100 na the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v ref = fs set C zs set . (note 3) a alog i put a d refere ce u u u u 4 ltc2421/ltc2422 24212f the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) f eosc external oscillator frequency range l 2.56 307.2 khz t heo external oscillator high period l 0.5 390 m s t leo external oscillator low period l 0.5 390 m s t conv conversion time f o = 0v l 130.86 133.53 136.20 ms f o = v cc l 157.03 160.23 163.44 ms external oscillator (note 11) l 20510/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 10) 19.2 khz external oscillator (notes 10, 11) f eosc /8 khz d isck internal sck duty cycle (note 10) 45 55 % f esck external sck frequency range (note 9) l 2000 khz t lesck external sck low period (note 9) l 250 ns t hesck external sck high period (note 9) l 250 ns t dout_isck internal sck 24-bit data output time internal oscillator (notes 10, 12) l 1.23 1.25 1.28 ms external oscillator (notes 10, 11) l 192/f eosc (in khz) ms t dout_esck external sck 24-bit data output time (note 9) l 24/f esck (in khz) ms t 1 cs to sdo low z l 0 150 ns t 2 cs - to sdo high z l 0 150 ns t 3 cs to sck (note 10) l 0 150 ns t 4 cs to sck - (note 9) l 50 ns t kqmax sck to sdo valid l 200 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7 to 5.5v unless otherwise specified. input source resistance = 0 w . note 4: internal conversion clock source with the f o pin tied to gnd or to v cc or to external conversion clock source with f eosc = 153600hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f o = 0v (internal oscillator) or f eosc = 153600hz 2% (external oscillator). note 8: f o = v cc (internal oscillator) or f eosc = 128000hz 2% (external oscillator). note 9: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 10: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation, the sck pin has a total equivalent load capacitance c load = 20pf. note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. f o = 0v or f o = v cc . note 13: the output noise includes the contribution of the internal calibration operations. note 14: v ref = fs set C zs set . the minimum input voltage is limited to C 0.3v and the maximum to v cc + 0.3v. note 15: v cc (dc) = 4.1v, v cc (ac) = 2.8v p-p . ti i g characteristics u w 5 ltc2421/ltc2422 24212f typical perfor a ce characteristics uw total unadjusted error (3v supply) inl (3v supply) negative extended input range total unadjusted error (3v supply) positive extended input range total unadjusted error (3v supply) total unadjusted error (5v supply) inl (5v supply) negative extended input range total unadjusted error (5v supply) offset error vs reference voltage positive extended input range total unadjusted error (5v supply) input voltage (v) 0 error (ppm) 2 6 10 2.0 24212 g01 ? ? 0 4 8 ? ? ?0 0.5 1.0 1.5 2.5 v cc = 3v v ref = 2.5v t a = 55 c, 45 c, 25 c, 90 c input voltage (v) 0 error (ppm) 2 6 10 2.0 24212 g02 ? ? 0 4 8 ? ? ?0 0.5 1.0 1.5 2.5 v cc = 3v v ref = 2.5v t a = 55 c, 45 c, 25 c, 90 c input voltage (v) 0 ?0 ? ? 2 0.05 0.10 0.15 0.20 24212 g03 0.25 10 0.30 error (ppm) 6 ? ? 0 8 4 v cc = 3v v ref = 2.5v t a = 90 c t a = 25 c t a = 45 c t a = 55 c input voltage (v) 2.50 ?0 ? ? 2 2.55 2.60 2.65 2.70 24212 g04 2.75 10 2.80 error (ppm) 6 ? ? 0 8 4 v cc = 3v v ref = 2.5v t a = 55 c, ?5 c, 25 c, 90 c input voltage (v) 0 error (ppm) 2 6 10 4 24212 g05 ? ? 0 4 8 ? ? ?0 1 2 3 5 v cc = 5v v ref = 5v t a = 55 c, 45 c, 25 c, 90 c input voltage (v) 0 error (ppm) 2 6 10 4 24212 g06 ? ? 0 4 8 ? ? ?0 1 2 3 5 v cc = 5v v ref = 5v t a = 55 c, 45 c, 25 c, 90 c input voltage (v) 0 ?0 ? ? 2 0.05 0.10 0.15 0.20 24212 g07 0.25 10 0.30 error (ppm) 6 ? ? 0 8 4 v cc = 5v v ref = 5v t a = 90 c t a = 25 c t a = 55 c t a = 45 c input voltage (v) 5.00 ?0 ? ? 2 5.05 5.10 5.15 5.20 24212 g08 5.25 10 5.30 error (ppm) 6 ? ? 0 8 4 v cc = 5v v ref = 5v t a = 45 c t a = 55 c t a = 25 c t a = 90 c reference voltage (v) 0 offset error (ppm) 90 120 150 4 24212 g09 60 30 0 1 2 3 5 v cc = 5v t a = 25 c 6 ltc2421/ltc2422 24212f typical perfor a ce characteristics uw rms noise vs reference voltage offset error vs v cc rms noise vs v cc noise histogram rms noise vs code out offset error vs temperature full-scale error vs temperature full-scale error vs reference voltage full-scale error vs v cc reference voltage (v) 0 0 rms noise (ppm of v ref ) 10 20 30 40 50 60 1234 24212 g10 5 v cc = 5v t a = 25 c v cc (v) 2.7 ?0 offset error (ppm) ? 0 5 10 3.2 3.7 4.2 4.7 24212 g11 5.2 5.5 v ref = 2.5v t a = 25 c v cc (v) 2.7 0 rms noise (ppm) 2.5 5.0 7.5 10.0 3.2 3.7 4.2 4.7 24212 g12 5.2 5.5 v ref = 2.5v t a = 25 c output code (ppm) 0 50 100 150 200 250 300 350 26 24212 g13 ? 0 4 number of readings v cc = 5 v ref = 5 v in = 0 code out (hex) 0 7ffff fffff 0 rms noise (ppm) 1.25 2.50 3.75 5.00 24212 g14 v cc = 5v v ref = 5v v in = 0.3v to 5.3v t a = 25 c temperature ( c) ?5 ?0 offset error (ppm) ? 0 5 10 ?0 5 20 45 24212 g15 70 95 120 v cc = 5v v ref = 5v v in = 0v temperature ( c) ?5 ?0 full-scale error (ppm) ? 0 5 10 ?0 5 20 45 24212 g16 70 95 120 v cc = 5v v ref = 5v v in = 5v reference voltage (v) 0 150 full-scale error (ppm) 125 100 ?5 ?0 ?5 0 1234 24212 g17 5 v cc = 5v v in = v ref v cc (v) 2.7 ?0 full-scale error (ppm) ? 0 5 10 3.2 3.7 4.2 4.7 24212 g18 5.2 5.5 v ref = 2.5v v in = 2.5v t a = 25 c 7 ltc2421/ltc2422 24212f typical perfor a ce characteristics uw conversion current vs temperature sleep current vs temperature rejection vs frequency at v in rejection vs frequency at v in rejection vs frequency at v in rejection vs frequency at v in rejection vs frequency at v cc rejection vs frequency at v cc rejection vs frequency at v cc temperature ( c) ?5 supply current ( a) 220 20 24212 g19 190 170 ?0 5 45 160 150 230 210 200 180 70 95 120 v cc = 5.5v v cc = 4.1v v cc = 2.7v temperature ( c) ?5 0 supply current ( m a) 10 20 30 ?0 5 20 45 24212 g20 70 95 120 v cc = 2.7v v cc = 5v frequency at v cc (hz) 1 rejection (db) ?0 ?0 ?0 200 24212 g21 ?0 ?00 ?20 50 100 150 250 v cc = 4.1v v in = 0v t a = 25 c f o = 0 frequency at v cc (hz) 15200 120 rejection (db) 100 ?0 ?0 ?0 0 15250 15300 15350 15400 24212 g22 15450 15500 ?0 v cc = 4.1v v in = 0v t a = 25 c f o = 0 frequency at v cc (hz) 1 ?20 rejection (db) ?00 ?0 ?0 ?0 ?0 0 100 10k 1m 24212 g23 v cc = 4.1v v in = 0v t a = 25 c f o = 0 frequency at v in (hz) 1 120 rejection (db) 100 ?0 ?0 ?0 ?0 0 50 100 150 200 24212 g24 250 v cc = 5v v ref = 5v v in = 2.5v f o = 0 input frequency deviation from notch frequency (%) 12 8 404812 rejection (db) 24212 g25 ?0 ?0 ?0 ?0 100 110 120 130 140 frequency at v in (hz) 15100 120 rejection (db) 100 ?0 ?0 ?0 ?0 0 15200 15300 15400 15500 24212 g26 v cc = 5v v ref = 5v v in = 2.5v f o = 0 sample rate = 15.36khz 2% input frequency 0 ?0 ?0 0 24212 g27 ?0 100 f s /2 f s 120 140 ?0 rejection (db) 8 ltc2421/ltc2422 24212f typical perfor a ce characteristics uw pi n fu n ctio n s uuu v cc (pin 1): positive supply voltage. bypass to gnd (pin 6) with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. fs set (pin 2): full-scale set input. this pin defines the full-scale input value. when v in = fs set , the adc outputs full scale (fffff h ). the total reference voltage is fs set C zs set . ch0, ch1 (pins 4, 3): analog input channels. the input voltage range is C 0.125 ? v ref to 1.125 ? v ref . for v ref > 2.5v, the input voltage range may be limited by the absolute maximum rating of C 0.3v to v cc + 0.3v. conver- sions are performed alternately between ch0 and ch1 for the ltc2422. pin 4 is a no connect (nc) on the ltc2421. zs set (pin 5): zero-scale set input. this pin defines the zero-scale input value. when v in = zs set , the adc outputs zero scale (00000 h ). gnd (pin 6): ground. shared pin for analog ground, digital ground, reference ground and signal ground. should be connected directly to a ground plane through a mini- mum length trace or it should be the single-point-ground in a single-point grounding system. cs (pin 7): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion, the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low on cs wakes up the adc. a low-to-high transition on this pin disables the sdo digital output. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 8): three-state digital output. during the data output period, this pin is used for serial data output. when the chip select cs is high (cs = v cc ), the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin can be used as a conversion status out- put. the conversion status can be observed by pulling cs low. inl vs output rate resolution vs output rate output rate (hz) 0 tue resolution (bits) 16 18 20 40 24212 g28 14 12 10 10 20 30 50 60 70 80 90 100 v cc = 5v v ref = 5v f o = external t a = 45 c t a = 25 c t a = 90 c output rate (hz) 0 tue resolution (bits) 16 18 20 40 24212 g29 14 12 10 10 20 30 50 60 70 80 90 100 v cc = 3v v ref = 2.5v f o = external t a = 45 c t a = 25 c t a = 90 c output rate (hz) 0 7.5 effective resolution (bits) 20 22 75 24212 g30 18 16 25 50 100 24 t a = 25 c t a = 90 c t a = 45 c v cc = 5v v ref = 5v f o = external standard deviation of 100 samples inl vs output rate 9 ltc2421/ltc2422 24212f pi n fu n ctio n s uu u sck (pin 9): bidirectional digital clock pin. in the internal serial clock operation mode, sck is used as digital output for the internal serial interface clock during the data output period. in the external serial clock operation mode, sck is used as digital input for the external serial interface. an internal pull-up current source is automatically activated in internal serial clock operation mode. the serial clock mode is determined by the level applied to sck at power up and the falling edge of cs. f o (pin 10): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to v cc (f o = v cc ), the converter uses its internal oscillator and the digital filters first null is located at 50hz. when the f o pin is connected to gnd (f o = 0v), the converter uses its internal oscillator and the digital filters first null is located at 60hz. when f o is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its clock and the digital filter first null is located at a frequency f eosc /2560. fu n ctio n al block diagra uu w test circuits 3.4k sdo 24212 tc01 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 3.4k sdo 24212 tc02 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc autocalibration and control dac decimating fir internal oscillator serial interface adc gnd v cc v in sdo sck v ref cs f o (int/ext) 24212 fd 10 ltc2421/ltc2422 24212f applicatio s i for atio wu uu the ltc2421/ltc2422 are pin compatible with the ltc2401/ltc2402. the devices are designed to allow the user to incorporate either device in the same design with no modifications. while the ltc2421/ltc2422 output word length is 24 bits (as opposed to the 32-bit output of the ltc2401/ltc2402), its output clock timing can be identi- cal to the ltc2401/ltc2402. as shown in figure 1, the ltc2421/ltc2422 data output is concluded on the falling edge of the 24th serial clock (sck). in order to maintain drop-in compatibility with the ltc2401/ltc2402, it is possible to clock the ltc2421/ltc2422 with an additional 8 serial clock pulses. this results in 8 additional output bits which are always logic high. converter operation cycle the ltc2421/ltc2422 are low power, delta-sigma ana- log-to-digital converters with an easy to use 3-wire serial interface. their operation is simple and made up of three states. the converter operating cycle begins with the con- version, followed by the sleep state and concluded with the data output (see figure 2). the 3-wire interface consists of serial data output (sdo), a serial clock (sck) and a chip select (cs). initially, the ltc2421/ltc2422 perform a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is re- duced by an order of magnitude if cs is high. the part remains in the sleep state as long as cs is logic high. the conversion result is held indefinitely in a static shift regis- ter while the converter is in the sleep state. figure 1. ltc2421/ltc2422 compatible timing with the ltc2401/ltc2402 cs sck sdo conversion sleep 8 8 8 8 (optional) eoc = 1 eoc = 1 last 8 bits always 1 eoc = 0 data out 4 status bits 20 data bits data output 24212 f01 conversion convert sleep data output 24212 f02 0 1 cs and sck figure 2. ltc2421/ltc2422 state transition diagram once cs is pulled low and sck rising edge is applied, the device begins outputting the conversion result. there is no latency in the conversion result. the data output corre- sponds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the control of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck, see figure 4. the data output state is concluded once 24 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs and sck pins, the ltc2421/ltc2422 offer several flexible modes of opera- tion (internal or external sck and free-running conver- sion modes). these various modes do not require program ming configuration registers; moreover, they do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. 11 ltc2421/ltc2422 24212f conversion clock a major advantage delta-sigma converters offer over con- ventional type converters is an on-chip digital filter (com- monly known as sinc or comb filter). for high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50hz or 60hz plus their har- monics. in order to reject these frequencies in excess of 110db, a highly accurate conversion clock is required. the ltc2421/ltc2422 incorporate an on-chip highly accu- rate oscillator. this eliminates the need for external fre- quency setting components such as crystals or oscilla- tors. clocked by the on-chip oscillator, the ltc2421/ ltc2422 reject line frequencies (50hz or 60hz 2%) a minimum of 110db. ease of use the ltc2421/ltc2422 data output has no latency, filter settling or redundant data associated with the conver- sion cycle. there is a one-to-one correspondence be- tween the conversion and the output data. therefore, multiplexing an analog input voltage is easy. the ltc2421/ltc2422 perform offset and full-scale cali- brations every conversion cycle. this calibration is trans- parent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. power-up sequence the ltc2421/ltc2422 automatically enter an internal reset state when the power supply voltage v cc drops below approximately 2.2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selection which is performed at the initial power-up. (see the 2-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with duration of approximately 0.5ms. the por signal clears all internal registers. following the por sig- nal, the ltc2421/ltc2422 start a normal conversion cycle and follows the normal succession of states described applicatio s i for atio wu uu above. the first conversion result following por is accu- rate within the specifications of the device. reference voltage range the ltc2421/ltc2422 can accept a reference voltage (v ref = fs set C zs set ) from 0v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly con- stant with reference voltage. a decrease in reference volt- age will not significantly improve the converters effective resolution. on the other hand, a reduced reference voltage will improve the overall converter inl performance. the recommended range for the ltc2421/ltc2422 voltage reference is 100mv to v cc . input voltage range the converter is able to accommodate system level offset and gain errors as well as system level overrange situa- tions due to its extended input range, see figure 3. the ltc2421/ltc2422 convert input signals within the ex- tended input range of C 0.125 ? v ref to 1.125 ? v ref (v ref = fs set C zs set ). for large values of v ref (v ref = fs set C zs set ), this range is limited by the absolute maximum voltage range of C 0.3v to (v cc + 0.3v). beyond this range, the input esd protection devices begin to turn on and the errors due to the input leakage current increase rapidly. input signals applied to v in may extend below ground by C 300mv and above v cc by 300mv. in order to limit any figure 3. ltc2421/ltc2422 input range 24212 f03 v cc + 0.3v fs set + 0.12v ref fs set 0.3v (v ref = fs set ?zs set ) zs set ?0.12v ref zs set normal input range extended input range absolute maximum input range 12 ltc2421/ltc2422 24212f applicatio s i for atio wu uu figure 4. output data timing fault current, a resistor of up to 5k may be added in series with the v in pin without affecting the performance of the device. in the physical layout, it is important to maintain the parasitic capacitance of the connection between this series resistance and the v in pin as low as possible; there- fore, the resistor should be located as close as practical to the v in pin. the effect of the series resistance on the con- verter accuracy can be evaluated from the curves pre- sented in the analog input/reference current section. in addition, a series resistor will introduce a temperature de- pendent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. output data format the ltc2421/ltc2422 serial output data stream is 24 bits long. the first 4 bits represent status information indicat- ing the sign, selected channel, input range and conversion state. the next 20 bits are the conversion result, msb first. bit 23 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 22 (second output bit) for the ltc2422, this bit is low if the last conversion was performed on ch0 and high for ch1. this bit is always low for the ltc2421. bit 21 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. the sign bit changes state during the zero code. bit 20 (fourth output bit) is the extended input range (exr) indicator. if the input is within the normal input range 0 v in v ref , this bit is low. if the input is outside the normal input range, v in > v ref or v in < 0, this bit is high. the function of these bits is summarized in table 1. table 1. ltc2421/ltc2422 status bits bit 23 bit 22 bit 21 bit 20 input range eoc ch0/ch1 sig exr v in > v ref 0 *0/1 1 1 0 < v in v ref 0 *0/1 1 0 v in = 0 + /0 C 0 *0/1 1/0 0 v in < 0 0 *0/1 0 1 *bit 22 displays the channel number for the ltc2422. bit 22 is always 0 for the ltc2421 bit 19 (fifth output bit) is the most significant bit (msb). bits 19-0 are the 20-bit conversion result msb first. bit 0 is the least significant bit (lsb). data is shifted out of the sdo pin under control of the serial clock (sck), see figure 4. whenever cs is high, sdo remains high impedance and any sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this sig- nal may be used as an interrupt for an external microcon- troller. bit 23 (eoc) can be captured on the first rising edge of sck. bit 22 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 23rd sck and may be latched on the rising edge of the 24th sck pulse. on the falling edge of the 24th sck pulse, sdo goes high indicating a new conver- sion cycle has been initiated. this bit serves as eoc (bit 23) for the next conversion cycle. table 2 summarizes the output data format. msb ext sig ch0/ch1 1 2 3 4 5 192024 bit 0 bit 19 bit 4 lsb 20 bit 20 bit 21 bit 22 sdo sck cs eoc bit 23 sleep data output conversion 24212 f04 hi-z 13 ltc2421/ltc2422 24212f applicatio s i for atio wu uu as long as the voltage on the v in pin is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any input value from C 0.125 ? v ref to 1.125 ? v ref . for input voltages greater than 1.125 ? v ref , the conversion result is clamped to the value corresponding to 1.125 ? v ref . for input volt- ages below C 0.125 ? v ref , the conversion result is clamped to the value corresponding to C 0.125 ? v ref . frequency rejection selection (f o pin connection) the ltc2421/ltc2422 internal oscillator provides better than 110db normal mode rejection at the line frequency and all its harmonics for 50hz 2% or 60hz 2%. for 60hz rejection, f o (pin 10) should be connected to gnd (pin 6) while for 50hz rejection the f o pin should be con- nected to v cc (pin 1). the selection of 50hz or 60hz rejection can also be made by driving f o to an appropriate logic level. a selection change during the sleep or data output states will not disturb the converter operation. if the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. when a fundamental rejection frequency different from 50hz or 60hz is required or when the converter must be synchronized with an outside source, the ltc2421/ ltc2422 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 2560hz (1hz notch frequency) to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2421/ltc2422 provide better than 110db normal mode rejection in a frequency range f eosc / 2560 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc / 2560 is shown in figure 5. whenever an external clock is not present at the f o pin, the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2421/ ltc2422 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an table 2. ltc2421/ltc2422 output data format bit 23 bit 22* bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 0 input voltage eoc ch0/ch1 sig exr msb lsb v in > 9/8 ? v ref 0 ch0/ch1 1100 0 11...1 9/8 ? v ref 0 ch0/ch1 1100 0 11...1 v ref + 1lsb 0 ch0/ch1 1100 0 00...0 v ref 0 ch0/ch1 1011 1 11...1 3/4v ref + 1lsb 0 ch0/ch1 1011 0 00...0 3/4v ref 0 ch0/ch1 1010 1 11...1 1/2v ref + 1lsb 0 ch0/ch1 1010 0 00...0 1/2v ref 0 ch0/ch1 1001 1 11...1 1/4v ref + 1lsb 0 ch0/ch1 1001 0 00...0 1/4v ref 0 ch0/ch1 1000 1 11...1 0 + /0 C 0 ch0/ch1 1/0** 0 0 0 0 0 0 ... 0 C1lsb 0 ch0/ch1 0111 1 11...1 C1/8 ? v ref 0 ch0/ch1 0111 1 00...0 v in < C1/8 ? v ref 0 ch0/ch1 0111 1 00...0 *bit 22 is always 0 for the ltc2421 **the sign bit changes state during the 0 code. 14 ltc2421/ltc2422 24212f external serial clock. if the change occurs during the con- version state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3 summarizes the duration of each state as a func- tion of f o . serial interface the ltc2421/ltc2422 transmit the conversion results and receives the start of conversion command through a synchronous 3-wire interface. during the conversion and sleep states, this interface can be used to assess the con- verter status and during the data output state, it is used to read the conversion result. serial clock input/output (sck) the serial clock signal present on sck (pin 9) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2421/ltc2422 create their own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is detected at the cs pin. if sck is high or floating at power-up or during this transition, the con- verter enters the internal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. serial data output (sdo) the serial data output pin, sdo (pin 8), drives the serial data during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the con- version and sleep states. when cs (pin 7) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial table 3. ltc2421/ltc2422 state duration state operating mode duration convert internal oscillator f o = low 133ms (60hz rejection) f o = high 160ms (50hz rejection) external oscillator f o = external oscillator 20510/f eosc s with frequency f eosc khz (f eosc /2560 rejection) sleep as long as cs = high until cs = 0 and sck data output internal serial clock f o = low/high as long as cs = low but not longer than 1.28ms (internal oscillator) (24 sck cycles) f o = external oscillator with as long as cs = low but not longer than 192/f eosc ms frequency f eosc khz (24 sck cycles) external serial clock with as long as cs = low but not longer than 24/f sck ms frequency f sck khz (24 sck cycles) applicatio s i for atio wu uu figure 5. ltc2421/ltc2422 normal mode rejection when using an external oscillator of frequency f eosc input frequency deviation from notch frequency (%) 12 8 404812 rejection (db) 24212 f05 ?0 ?0 ?0 ?0 100 110 120 130 140 15 ltc2421/ltc2422 24212f interface with other devices. if cs is low during the con- vert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while cs = 0. while in the sleep state, the device is in a low power state if cs is high. chip select input (cs) the active low chip select, cs (pin 7), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2421/ltc2422 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state (i.e., after the first rising edge of sck occurs with cs = 0). finally, cs can be used to control the free-running modes of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . tying a ca- pacitor to cs will reduce the output rate and power dissi- pation by a factor proportional to the capacitors value, see figures 13 to 15. serial interface timing modes the ltc2421/ltc2422s 3-wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/exter- nal serial clock, 2- or 3-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 4 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and con- trol the state of the conversion cycle, see figure 6. the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. independent of cs, the device auto- matically enters the sleep state once the conversion is complete. while in the sleep state, power is reduced an order of magnitude if cs is high. when the device is in the sleep state (eoc = 0), its conversion result is held in an internal static shift register. the device remains in the sleep state until the first rising edge of sck is seen while cs is low. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 24th rising edge of sck. on the 24th falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. table 4. ltc2421/ltc2422 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 6, 7 external sck, 2-wire i/o external sck sck figure 8 internal sck, single cycle conversion internal cs cs figures 9, 10 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 11 internal sck, autostart conversion internal c ext internal figure 12 applicatio s i for atio wu uu 16 ltc2421/ltc2422 24212f applicatio s i for atio wu uu at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling figure 6. external serial clock, single cycle operation v cc f o fs set zs set sck ch1 sdo gnd cs reference voltage zs set + 0.1v to v cc 0v to fs set ? 100mv ch0 = internal osc/50hz rejection = external clock source = internal osc/60hz rejection 1 f 110 9 8 7 6 2 3 4 5 2.7v to 5.5v ltc2422 v cc 3-wire serial i/o analog input range zs set ?0.12v ref to fs set + 0.12v ref (v ref = fs set ? zs set ) eoc ch0/ch1 bit 23 sdo sck (external) cs test eoc msb lsb 20 exr sig bit 0 bit 4 bit 19 bit 18 bit 20 bit 21 bit 22 sleep data output conversion 24212 f06 conversion hi-z hi-z hi-z test eoc test eoc cs high anytime between the first rising edge and the 24th falling edge of sck, see figure 7. on the rising edge of cs, the device aborts the data output state and imme- diately initiates a new conversion. this is useful for sys- tems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. figure 7. external serial clock, reduced data output length v cc f o fs set zs set sck ch1 sdo gnd cs reference voltage zs set + 0.1v to v cc 0v to fs set ? 100mv ch0 = internal osc/50hz rejection = external clock source = internal osc/60hz rejection 1 f 110 9 8 7 6 2 3 4 5 2.7v to 5.5v ltc2422 v cc 3-wire serial i/o analog input range zs set ?0.12v ref to fs set + 0.12v ref (v ref = fs set ? zs set ) sdo sck (external) cs data output conversion sleep sleep test eoc test eoc data output hi-z hi-z hi-z conversion 24212 f07 msb exr sig bit 8 bit 19 bit 9 bit 20 bit 21 bit 22 eoc ch0/ch1 bit 23 bit 0 eoc hi-z test eoc 17 ltc2421/ltc2422 24212f external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 8. cs may be permanently tied to ground (pin 6), simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 0.5ms after v cc exceeds 2.2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an inter- rupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion enters the low power sleep state. on the falling edge of eoc, the conversion result is loaded into an internal static shift register. the device remains in the sleep state until the first rising edge of sck. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the first rising edge of sck. on the 24th falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and con- trol the state of the conversion cycle, see figure 9. in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of cs. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs. an internal weak pull-up resistor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is auto- matically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state if cs remains low. in order to prevent the device from exiting the low power sleep state, cs must be pulled applicatio s i for atio wu uu figure 8. external serial clock, cs = 0 operation v cc f o fs set zs set sck ch1 sdo gnd cs reference voltage zs set + 0.1v to v cc 0v to fs set ? 100mv ch0 = internal osc/50hz rejection = external clock source = internal osc/60hz rejection 1 f 110 9 2-wire serial i/o 8 7 6 2 3 4 5 2.7v to 5.5v ltc2422 v cc analog input range zs set ?0.12v ref to fs set + 0.12v ref (v ref = fs set ? zs set ) eoc ch0/ch1 bit 23 sdo sck (external) cs msb exr sig bit 0 lsb 20 bit 4 bit 19 bit 18 bit 20 bit 21 bit 22 sleep data output conversion 24212 f08 conversion 18 ltc2421/ltc2422 24212f applicatio s i for atio wu uu high before the first rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 23 m s if the device is using its internal oscillator (f 0 = logic low or high). if f o is driven by an external oscillator of fre- quency f eosc , then t eoctest is 3.6/f eosc . if cs is pulled high before time t eoctest , the device remains in the sleep state. the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the first rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data output cycle begins on this first rising edge of sck and concludes after the 24th rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the con- version result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the con- version result on the 24th rising edge of sck. after the 24th rising edge, sdo goes high (eoc = 1), sck stays high, and a new conversion starts. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first and 24th rising edge of sck, see figure 10. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. if cs is pulled high while the converter is driving sck low, the internal pull-up is not available to restore sck to a logic high state. this will cause the device to exit the internal serial clock mode on the next falling edge of cs. this can be avoided by adding an external 10k pull-up resistor to the sck pin or by never pulling cs high when sck is low. whenever sck is low, the ltc2421/ltc2422s internal pull-up at pin sck is disabled. normally, sck is not exter- nally driven if the device is in the internal sck timing mode. however, certain applications may require an external driver on sck. if this driver goes hi-z after outputting a low signal, the ltc2421/ltc2422s internal pull-up remains disabled. hence, sck remains low. on the next falling edge of cs, the device is switched to the external sck timing mode. by adding an external 10k pull-up resistor to sck, this pin goes high once the external driver goes hi-z. on the next cs falling edge, the device will remain in the internal sck timing mode. figure 9. internal serial clock, single cycle operation v cc 10k v cc f o fs set zs set sck ch1 sdo gnd cs reference voltage zs set + 0.1v to v cc 0v to fs set ? 100mv ch0 = internal osc/50hz rejection = external clock source = internal osc/60hz rejection 1 f 110 9 8 7 6 2 3 4 5 2.7v to 5.5v ltc2422 v cc analog input range zs set ?0.12v ref to fs set + 0.12v ref (v ref = fs set ? zs set ) sdo sck (internal) cs msb exr sig bit 0 lsb 20 bit 4 test eoc bit 19 bit 18 bit 20 bit 21 bit 22 eoc ch0/ch1 bit 23 sleep data output conversion conversion 24212 f09 21 ltc2421/ltc2422 24212f applicatio s i for atio wu uu figure 12. internal serial clock, autostart operation v cc f o fs set zs set sck ch1 sdo gnd cs reference voltage zs set + 0.1v to v cc 0v to fs set ? 100mv ch0 = internal osc/50hz rejection = external clock source = internal osc/60hz rejection 1 f 110 9 8 7 6 c ext 2 3 4 5 2.7v to 5.5v ltc2422 v cc v cc 10k analog input range zs set ?0.12v ref to fs set + 0.12v ref (v ref = fs set ? zs set ) sdo hi-z hi-z sck (internal) cs v cc gnd 2420 f12 bit 0 sig bit 21 bit 22 sleep data output conversion conversion eoc bit 23 figure 13. cs capacitance vs t sample figure 14. cs capacitance vs output rate capacitance on cs (pf) 1 5 6 7 1000 10000 24212 f13 4 3 10 100 100000 2 1 0 t sample (sec) v cc = 5v v cc = 3v capacitance on cs (pf) 1 0 supply current ( a rms ) 50 100 150 200 250 300 10 100 1000 10000 24212 f15 100000 v cc = 5v v cc = 3v to take advantage of exceptional accuracy and low supply current. the digital output signals (sdo and sck in internal sck mode of operation) are less of a concern because they are not generally active during the conversion state. in order to preserve the ltc2421/ltc2422s accuracy, it is very important to minimize the ground path impedance which may appear in series with the input and/or reference signal and to reduce the current which may flow through this path. the gnd pin should be connected to a low capacitance on cs (pf) 1 0 supply current ( a rms ) 50 100 150 200 250 300 10 100 1000 10000 24212 f15 100000 v cc = 5v v cc = 3v figure 15. cs capacitance vs supply current 22 ltc2421/ltc2422 24212f resis tance ground plane through a minimum length trace. the use of multiple via holes is recommended to further reduce the connection resistance. in an alternative configuration, the gnd pin of the con- verter can be the single-point-ground in a single point grounding system. the input signal ground, the reference signal ground, the digital drivers ground (usually the digi- tal ground) and the power supply ground (the analog ground) should be connected in a star configuration with the common point located as close to the gnd pin as possible. the power supply current during the conversion state should be kept to a minimum. this is achieved by restrict- ing the number of digital signal transitions occurring dur- ing this period. while a digital input signal is in the range 0.5v to (v cc C 0.5v), the cmos input receiver draws additional current from the power supply. it should be noted that, when any one of the digital input signals (f o , cs and sck in external sck mode of operation) is within this range, the ltc2421/ltc2422 power supply current may increase even if the signal in question is at a valid logic level. for micropower operation and in order to minimize the poten- tial errors due to additional ground pin current, it is recom- mended to drive all digital input signals to full cmos levels [v il < 0.4v and v oh > (v cc C 0.4v)]. severe ground pin current disturbances can also occur due to the undershoot of fast digital input signals. under- shoot and overshoot can occur because of the imped- ance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to ltc2421/ltc2422. for reference, on a regular fr-4 board, signal propaga- tion velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. this problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. the solution is to carefully terminate all transmission lines close to their characteristic impedance. applicatio s i for atio wu uu parallel termination near the ltc2421/ltc2422 pin will eliminate this problem but will increase the driver power dissipation. a series resistor between 27 w and 56 w placed near the driver or near the ltc2421/ltc2422 pin will also eliminate this problem without additional power dissipa- tion. the actual resistor value depends upon the trace impedance and connection topology. driving the input and reference the analog input and reference of the typical delta-sigma analog-to-digital converter are applied to a switched ca- pacitor network. this network consists of capacitors switch- ing between the analog input (v in ), zs set (pin 5) and fs set (pin 2). the result is small current spikes seen at both v in and v ref . a simplified input equivalent circuit is shown in figure 16. the key to understanding the effects of this dynamic input current is based on a simple first order rc time constant model. using the internal oscillator, the ltc2421/ ltc2422s internal switched capacitor network is clocked at 153,600hz corresponding to a 6.5 m s sampling period. fourteen time constants are required each time a capacitor is switched in order to achieve 1ppm settling accuracy. therefore, the equivalent time constant at v in and v ref should be less than 6.5 m s/14 = 460ns in order to achieve 1ppm accuracy. figure 16. ltc2421/ltc2422 equivalent analog input circuit v ref v in v cc r sw 5k average input current: i in = 0.25(v in ?0.5 ?v ref )fc eq i ref(leak) i ref(leak) v cc r sw 5k c eq 1pf (typ) r sw 5k i in(leak) i in 24212 f16 i in(leak) switching frequency f = 153.6khz for internal oscillator (f o = logic low or high) f = f eosc for external oscillators gnd 23 ltc2421/ltc2422 24212f input current (v in ) if complete settling occurs on the input, conversion re- sults will be uneffected by the dynamic input current. if the settling is incomplete, it does not degrade the linearity performance of the device. it simply results in an offset/ full-scale shift, see figure 17. to simplify the analysis of input dynamic current, two separate cases are assumed: large capacitance at v in (c in > 0.01 m f) and small capaci- tance at v in (c in < 0.01 m f). if the total capacitance at v in (see figure 18) is small (< 0.01 m f), relatively large external source resistances (up to 80k for 20pf parasitic capacitance) can be tolerated without any offset/full-scale error. figures 19 and 20 show a family of offset and full-scale error curves for various small valued input capacitors (c in < 0.01 m f) as a function of input source resistance. for large input capacitor values (c in > 0.01 m f), the input spikes are averaged by the capacitor into a dc current. the gain shift becomes a linear function of input source resis- tance independent of input capacitance, see figures 21 and 22. the equivalent input impedance is 16.6m w . this results in 150na of input dynamic current at the extreme values of v in (v in = 0v and v in = v ref , when v ref = 5v). this corresponds to a 0.3ppm shift in offset and full-scale readings for every 10 w of input source resistance. applicatio s i for atio wu uu figure 18. an rc network at v in figure 19. offset vs r source (small c) figure 17. offset/full-scale shift zs set tue v in 24212 f17 fs set c in 24212 f17 intput signal source r source v in ltc2421/ ltc2422 c par @ 20pf r source ( ) 1 offset error (ppm) 30 40 50 10k 24212 f19 20 10 0 10 100 1k 100k v cc = 5v v ref = 5v v in = 0v t a = 25 c c in = 100pf c in = 1000pf c in = 0pf c in = 0.01 f figure 20. offset vs r source (large c) figure 21. full-scale error vs r source (large c) r source ( ) 0 25 30 35 600 800 24212 f20 20 15 200 400 1000 10 5 0 offset error (ppm) c in = 22 f c in = 10 f c in = 1 f c in = 0.1 f c in = 0.01 f c in = 0.001 f v cc = 5v v ref = 5v v in = 0v t a = 25 c r source ( ) 0 full-scale error (ppm) ?0 ?5 ?0 600 1000 24212 f21 ?5 ?0 ?5 200 400 800 ? 0 5 c in = 22 f c in = 10 f c in = 1 f c in = 0.1 f c in = 0.01 f c in = 0.001 f v cc = 5v v ref = 5v v in = 0v t a = 25 c 24 ltc2421/ltc2422 24212f in addition to the input current spikes, the input esd pro- tection diodes have a temperature dependent leakage cur- rent. this leakage current, nominally 1na ( 100na max), results in a fixed offset shift of 10 m v for a 10k source resistance. the effect of input leakage current is evident for c in = 0 in figures 19 and 22. a leakage current of 3na results in a 150 m v (30ppm) error for a 50k source resistance. as r source gets larger, the switched capacitor input current begins to dominate. reference current (v ref ) similar to the analog input, the reference input has a dy- namic input current. this current has negligible effect on the offset. however, the reference current at v in = v ref is similar to the input current at full-scale. for large values of reference capacitance (c vref > 0.01 m f), the full-scale er- ror shift is 0.03ppm/ w of external reference resistance independent of the capacitance at v ref , see figure 23. if the capacitance tied to v ref is small (c vref < 0.01 m f), an input resistance of up to 80k (20pf parasitic capacitance at v ref ) may be tolerated, see figure 24. unlike the analog input, the integral nonlinearity of the device can be degraded with excessive external rc time constants tied to the reference input. if the capacitance at node v ref is small (c vref < 0.01 m f), the reference input can tolerate large external resistances without reduction in inl, see figure 25. if the external capacitance is large (c vref > 0.01 m f), the linearity will be degraded by applicatio s i for atio wu uu r source ( ) 1 ?0 full-scale error (ppm) ?0 ?0 ?0 ?0 0 10 10 100 1k 10k 24212 f22 100k v cc = 5v v ref = 5v v in = 5v t a = 25 c c in = 0.01 f c in = 100pf c in = 1000pf c in = 0pf figure 22. full-scale error vs r source (small c) figure 23. full-scale error vs r vref (large c) figure 24. full-scale error vs r vref (small c) resistance at v ref ( ) 0 40 50 60 600 800 24212 f23 30 20 200 400 1000 10 0 ?0 full-scale error (ppm) c vref = 22 f c vref = 10 f c vref = 1 f c vref = 0.1 f c vref = 0.01 f c vref = 0.001 f v cc = 5v v ref = 5v v in = 5v t a = 25 c resistance at v ref ( ) 1 300 400 500 1k 10k 24212 f24 200 100 10 100 100k 0 100 200 full-scale error (ppm) v cc = 5v v ref = 5v v in = 5v t a = 25 c c vref = 0.01 f c vref = 100pf c vref = 1000pf c vref = 0pf figure 25. inl error vs r vref (small c) resistance at v ref ( ) 1 30 40 50 1k 10k 24212 f25 20 10 10 100 100k 0 ?0 ?0 inl error (ppm) v cc = 5v v ref = 5v t a = 25 c c vref = 0.01 f c vref = 1000pf c vref = 0pf c vref = 100pf 25 ltc2421/ltc2422 24212f 0.015ppm/ w independent of capacitance at v ref , see figure 26. in addition to the dynamic reference current, the v ref esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na ( 10na max), results in a fixed full-scale shift of 10 m v for a 10k source resistance. applicatio s i for atio wu uu the modulator contained within the ltc2421/ltc2422 can handle large-signal level perturbations without satu- rating. signal levels up to 40% of v ref do not saturate the analog modulator. these signals are limited by the input esd protection to 300mv below ground and 300mv above v cc . simple basic program for interfacing to the ltc2421/ltc2422 figure 26. inl error vs r vref (large c) resistance at v ref ( ) 0 6 8 10 600 800 24212 f26 4 2 ? ? ? ? ?0 200 400 1000 0 inl error (ppm) c vref = 22 f c vref = 10 f c vref = 1 f c vref = 0.1 f c vref = 0.01 f c vref = 0.001 f v cc = 5v v ref = 5v t a = 25 c antialiasing one of the advantages delta-sigma adcs offer over con- ventional adcs is on-chip digital filtering. combined with a large oversampling ratio, the ltc2421/ltc2422 signifi- cantly simplify antialiasing filter requirements. the digital filter provides very high rejection except at integer multiples of the modulator sampling frequency (f s ), see figure 27. the modulator sampling frequency is 256 ? f o , where f o is the notch frequency (typically 50hz or 60hz). the bandwidth of signals not rejected by the digital filter is narrow ( ? 0.2%) compared to the band- width of the frequencies rejected. as a result of the oversampling ratio (256) and the digital filter, minimal (if any) antialias filtering is required in front of the ltc2421/ltc2422. if passive rc components are placed in front of the ltc2421/ltc2422, the input dy- namic current should be considered (see input current section). in cases where large effective rc time constants are used, an external buffer amplifier may be required to minimize the effects of input dynamic current. figure 27. sinc 4 filter rejection input frequency 0 ?0 ?0 0 24212 f27 ?0 100 f s /2 f s 120 140 ?0 rejection (db) sck dtr pc serial port cts rts sdo ltc2421 ltc2422 cs 24212 f28 v ref v in gnd figure 28 tiny.bas v1.0 copyright (c) 2000 by j. a. dutra and ltc, all rights reseved' note this program generates 32 scks for compatibility to 24-bit parts 'for use with most ltc24xy demo boards designed for the pc com port, qbasic 'outputs are chan%,signneg%,d2400 (magnitude), ppm, and v (volts) cls : on error goto 4970 cport = 1: rem input "com port number "; cport gosub 1900: timestart$ = time$ mcr% = port + 4: msr% = port + 6 color 15: locate 3, 1: print "hit any key to stop "; for np = 1 to 2000: out port, c0%: next np: 'power via txd do: '-------------------------start loop here-------- 26 ltc2421/ltc2422 24212f applicatio s i for atio wu uu nummeas = nummeas + c1% locate 2, 2: print "scan#="; nummeas; " "; date$; " "; time$; out mcr%, c0%: 'initialize sclk=0 k1 = km: d2400 = 0: chan% = c0%: signneg% = c0% for bita% = 31 to 0 step -1: v31 = 1 148 gosub 2200: v31 = v31 + 1 150 if bita% = 31 then goto 152 else 156 152 if dfrm% = c0% then goto 156 155 if v31 > 2 then locate 16, 16: out port, c0%: print "waiting for eoc": if v31 < 20000 then if dfrm% = c1% then goto 148 if dfrm% = 1 then locate 17, 16: print "timed out on eoc,not fatal" for bs = 1 to 32: ' never got an eoc => clock it 32 times gosub 2000: next bs: goto 1800 156 locate 16, 16: print" ": gosub 2000 if bita% = 30 then 161 else 171 ' channel bit !!!!!!!!!!!!!!! 161 if dfrm% = c1% then chan% = c1%: ch1% = c0% if dfrm% = c0% then chan% = c0%: ch1% = ch1% + c1% if ch1% > c4% then gosub 3700: ch1% = c1% 171 if bita% = 29 then if dfrm% = c0% then signneg% = c1%: ' neg if bita% <= 28 then d2400 = d2400 + (dfrm% * k1): k1 = k1 / c2% next bita%: k1 = 1: digin% = c0%: 'math below 1600 ppm = (d2400 / km) * kn: rw% = 6: hz% = (chan% * 20) + 1 if signneg% = c1% then 1700 else 1705 1700 if d2400 <> c0% then ppm = (ppm - 2000000) 1705 locate rw%, hz%: print ppm; " "; : locate rw%, hz% + 11: print "ppm"; locate rw% + 1, (chan% * 20) + 1: gosub 3800: 'this works! 1800 loop while inkey$ = "": rem works with "do" goto 5000 rem end!!-------------- subs follow !!----------------!!! 1900 essential initializations rem set some constants, since they can be accessed much faster let c128% = 128: c64% = 64: c32% = 32: c16% = 16: c8% = 8: c4% = 4 let c3% = 3: c2% = 2: c1% = 1: c0% = 0: km = (2 ^ 30) - 1: kn = 1000000 if cport = 2 then open "com2:300,n,8,1,cd0,cs0,ds0,op0,rs" for random as #1: port = (&h2f8) if cport = 1 then open "com1:300,n,8,1,cd0,cs0,ds0,op0,rs" for random as #1: port = (&h3f8) locate 5, 21: print "channel 1": locate 5, 2: print "channel 0" for n% = port to port + 7: out n%, 0: next n%: init uart regs close #1: def seg = 0: return -------------------------------------- 2000 sub read msr and return data dfrm% interface x3% = inp(msr%) and c16%: out mcr%, c1% gosub 3000: out mcr%, c0% 2040 if x3% = c16% then dfrm% = c1% else dfrm% = c0% out mcr%, c0%: return --------------------------------------------- 2200 sub read the data bit dfrm% does not change sclock x3% = inp(msr%) and c16%: goto 2040: return---------------- 3000 rem delay sub !!!!!!!!!! for n8% = 0 to 1: out port, c0%: next n8%: return: ---------- 3700 for n = 6 to 9: locate n, 20 print " ": next n: return--------------------------- 3800 sub to convert ppm into volts and print it v = ppm * (5 / 1000000): v1 = v * 1000000: hz% = (chan% * 20) + 12 if v <= .1 then print v1; " "; : locate rw% + 1, hz%: print "uv " if v > .1 then print v; " "; : locate rw% + 1, hz%: print "volts"; return---------------------------------------------------------------- 4970 print "error !!!!!!!!!!!!!!!" 5000 print : locate 18, 1: print "ending!!": print "hit any key to exit." print "start ="; timestart$; " end = "; time$; " # samples ="; nummeas close #1: end single ended half-bridge digitizer with reference and ground sensing sensors convert real world phenomena (temperature, pres- sure, gas levels, etc.) into a voltage. typically, this voltage is generated by passing an excitation current through the sensor. the wires connecting the sensor to the adc form parasitic resistors r p1 and r p2 . the excitation current also flows through parasitic resistors r p1 and r p2 , as shown in figure 29. the voltage drop across these parasitic resis- tors leads to systematic offset and full-scale errors. in order to eliminate the errors associated with these para- sitic resistors, the ltc2421/ltc2422 include a full-scale set input (fs set ) and a zero-scale set input (zs set ). as shown in figure 30, the fs set pin acts as a zero current full-scale sense input. errors due to parasitic 27 ltc2421/ltc2422 24212f applicatio s i for atio wu uu re sistance r p1 in series with the half-bridge sensor are removed by the fs set input to the adc. the absolute full- scale output of the adc (data out = fffff hex ) will occur at v in = v b = fs set , see figure 31. similarly, the offset errors due to r p2 are removed by the ground sense input zs set . the absolute zero output of the adc (data out = 00000 hex ) occurs at v in = v a = zs set . parasitic resistors r p3 to r p5 have negligible errors due to the 1na (typ) leakage current at pins fs set , zs set and v in . the wide dynamic input range (C 300mv to 5.3v) and low noise (1.2ppm rms) enable the ltc2421 or the ltc2422 to directly digitize the output of the bridge sensor. the ltc2422 is ideal for applications requiring continu- ous monitoring of two input sensors. as shown in figure 32, the ltc2422 can monitor both a thermocouple temperature probe and a cold junction temperature sen- sor. absolute temperature measurements can be performed with a variety of thermocouples using digital cold junction compensation. figure 31. transfer curve with zero-scale and full-scale set figure 30. half-bridge digitizer with zero-scale and full-scale sense figure 29. errors due to excitation currents v full-scale error sensor sensor output r p1 i excitation + v offset error + + r p2 24212 f29 v cc ltc2421 fs set gnd sck v in sdo f o cs zs set 3-wire spi interface 1 9 8 7 10 24212 f03 2 3 5 r p2 r p5 i dc @ 0 r p1 v b v a 6 r p4 i dc @ 0 i excitation r p3 i dc @ 0 00000 h 12.5% under range adc data out fffff h zs set fs set v in 24212 f31 12.5% extended range figure 32. isolated temperature measurement v cc f o fs set zs set sck ch1 sdo gnd cs thermocouple cold junction isolation barrier processor ch0 + 110 12k thermistor 100 9 8 7 6 2 3 4 5 2.7v to 5.5v ltc2422 24212 f32 28 ltc2421/ltc2422 24212f applicatio s i for atio wu uu the selection between ch0 and ch1 is automatic. initially, after power-up, a conversion is performed on ch0. for each subsequent conversion, the input channel selection is alternated. embedded within the serial data output is a status bit indicating which channel corresponds to the conversion result. if the conversion was performed on ch0, this bit (bit 22) is low and is high if the conversion was performed on ch1 (see figure 33). there are no extra control or status pins required to per- form the alternating 2-channel measurements. the ltc2422 only requires two digital signals (sck and sdo). this simplification is ideal for isolated temperature mea- surements or systems where minimal control signals are available. pseudo differential applications generally, designers choose fully differential topologies for several reasons. first, the interface to a 4- or 6-wire bridge is simple (it is a differential output). second, they require good rejection of line frequency noise. third, they typically look at a small differential signal sitting on a large common mode voltage; they need accurate measurements of the differential signal independent of the common mode input voltage. many applications cur- rently using fully differential analog-to-digital converters for any of the above reasons may migrate to a pseudo differential conversion using the ltc2422. direct connection to a full bridge the ltc2422 interfaces directly to a 4- or 6-wire bridge, as shown in figure 34. the ltc2422 includes a fs set and a zs set for sensing the excitation voltage directly across the bridge. this eliminates errors due to excitation cur- rents flowing through parasitic resistors. the ltc2422 also includes two single ended input channels which can tie directly to the differential output of the bridge. the two conversion results may be digitally subtracted yielding the differential result. the ltc2422s single ended rejection of line frequencies ( 2%) and harmonics is better than 110db. since the device performs two independent single ended conver- sions each with > 110db rejection, the overall common mode and differential rejection is much better than the 80db rejection typically found in other differential input delta-sigma converters. in addition to excellent rejection of line frequency noise, the ltc2422 also exhibits excellent single ended noise rejection over a wide range of frequencies due to its 4 th order sinc filter. each single ended conversion indepen- dently rejects high frequency noise (> 60hz). care must be taken to insure noise at frequencies below 15hz and at multiples of the adc sample rate (15,360hz) are not present. for this application, it is recommended the ltc2422 is placed in close proximity to the bridge sensor in order to reduce the noise injected into the adc input. by performing three successive conversions (ch0-ch1-ch0), the drift and low frequency noise can be measured and compensated for digitally. figure 33. embedded selected channel indicator 24212 f33 sck sdo ch1 ? ? ? ch1 data out ch0 data out eoc ch0 eoc figure 34. pseudo differential strain guage application v cc ltc2422 fs set zs set sck ch1 sdo f o cs ch0 gnd 3-wire spi interface 1 5v 9 8 7 10 6 24212 f32 2 350 350 350 350 3 4 5 i dc = 0 i excitation i dc = 0 29 ltc2421/ltc2422 24212f applicatio s i for atio wu uu the absolute accuracy (less than 10 ppm total error) of the ltc2422 enables extremely accurate measurement of small signals sitting on large voltages. each of the two pseudo differential measurements performed by the ltc2422 is absolutely accurate independent of the com- mon mode voltage output from the bridge. the pseudo differential result obtained from digitally subtracting the two single ended conversion results is accurate to within the noise level of the device (3 m v rms ) times the square root of 2, independent of the common mode input voltage. typically, a bridge sensor outputs 2mv/v full scale. with a 5v excitation, this translates to a full-scale output of 10mv. divided by the rms noise of 8.4 m v(= 6 m v ? 1.414), this circuit yields 1190 counts with no averaging or ampli- fication. if more counts are required, several conversions may be averaged (the number of effective counts is in- creased by a factor of square root of 2 for each doubling of averages). an rtd temperature digitizer rtds used in remote temperature measurements often have long lead lengths between the adc and rtd sensor. these long lead lengths lead to voltage drops due to exci- tation current in the interconnect to the rtd. this voltage drop can be measured and digitally removed using the ltc2422 (see figure 35). the excitation current (typically 200 m a) flows from the adc through a long lead length to the remote temperature sensor (rtd). this current is applied to the rtd, whose resistance changes as a function of temperature (100 w to 400 w for 0 c to 800 c). the same excitation current flows back to the adc ground and generates another voltage drop across the return leads. in order to get an accurate measurement of the temperature, these voltage drops must be measured and removed from the conversion result. assuming the resistance is approximately the same for the forward and return paths (r1 = r2), the auxiliary channel on the ltc2422 can measure this drop. these errors are then removed with simple digital correction. the result of the first conversion on ch0 corresponds to an input voltage of v rtd + r1 ? i excitation. the result of the second conversion (ch1) is C r1 ? i excitation. note, the ltc2422s input range is not limited to the supply rails, it has underrange capabilities. the devices input range is C 300mv to v ref + 300mv. adding the two conversion results together, the voltage drop across the rtds leads are cancelled and the final result is v rtd . an isolated, 20-bit data acquisition system the ltc1535 is useful for signal isolation. figure 36 shows a fully isolated, 20-bit differential input a/d converter imple- mented with the ltc1535 and ltc2422. power on the isolated side is regulated by an lt1761-5.0 low noise, low dropout micropower regulator. its output is suitable for driving bridge circuits and for ratiometric applications. during power-up, the ltc2422 becomes active at v cc = 2.3v, while the isolated side of the ltc1535 must wait for v cc2 to reach its undervoltage lockout threshold of 4.2v. figure 35. rtd remote temperature measurement v cc ltc2422 fs set zs set sck ch0 sdo f o cs ch1 gnd 3-wire spi interface 1 5v 9 8 7 10 6 24212 f35 2 4 3 + v rtd p t 100 5 i dc = 0 i excitation = 200 a i excitation = 200 a r2 r1 5k 25 1000pf 5k 25 0.1 f 30 ltc2421/ltc2422 24212f applicatio s i for atio wu uu + + f o sck sdo cs gnd v cc fs set ch1 ch0 zs set ltc2422 24212 f36 lt1761-5 gnd 10 f 10v tant 10 f 10v tant + 10 f 16v tant + 10 f 10v tant 10 f 1 f t1 1/2 bat54c 1/2 bat54c isolation barrier = logic common = floating common t1 = coiltronics ctx02-14659 or siemens b78304-a1477-a3 1k 2 2 1 2 1 1 1 2 2 2 2 10 f ceramic a b y z ro re de di v cc2 st2 g1 v cc1 g2 st1 ?do ?ck logic 5v in out shdn byp ltc1535 figure 36. complete, isolated 20-bit data acquisition system below 4.2v, the ltc1535s driver outputs y and z are in a high impedance state, allowing the 1k w pull-down to de- fine the logic state at sck. when the ltc2422 first be- comes active, it samples sck; a logic 0 provided by the 1k w pull-down invokes the external serial clock mode. in this mode, the ltc2422 is controlled by a single clock line from the nonisolated side of the barrier, through the ltc1535s driver output y. the entire power-up sequence, from the time power is applied to v cc1 until the lt1761s output has reached 5v, is approximately 1ms. data returns to the nonisolated side through the ltc1535s receiver at ro. an internal divider on receiver input b sets a logic threshold of approximately 3.4v at input a, facili- tating communications with the ltc2422s sdo output without the need for any external components. 31 ltc2421/ltc2422 24212f package i for atio u u w information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) msop (ms) 1001 0.53 0.01 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) 0.13 0.05 (.005 .002) 0.86 (.034) ref 0.50 (.0197) typ 12 3 45 4.88 0.10 (.192 .004) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 3.05 0.38 (.0120 .0015) typ 0.50 (.0197) bsc 32 ltc2421/ltc2422 24212f lt/tp 0202 2k ? printed in usa ? linear technology corporation 2002 related parts part number description comments lt1019 precision bandgap reference, 2.5v, 5v 3ppm/ c drift, 0.05% max ltc1050 precision chopper stabilized op amp no external components 5 m v offset, 1.6 m v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/ c drift ltc1391 8-channel multiplexer low r on : 45 w , low charge injection serial interface lt1461-2.5 precision micropower voltage reference 50 m a supply current, 3ppm/ c drift ltc1535 isolated rs485 transceiver 2500v rms isolation ltc2400 24-bit, no latency ds adc in so-8 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2401/ltc2402 1-/2-channel, 24-bit, no latency ds adc in msop 0.6ppm noise, 4ppm inl, pin compatible with the ltc2421/ltc2422 ltc2404/ltc2408 4-/8-channel, 24-bit, no latency ds adc 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2413 24-bit, no latency ds adc simultaneous 50hz and 60hz rejection, 0.16ppm noise ltc2415 24-bit, fully differential, no latency ds adc 15hz output rate at 60hz rejection, pin conpatible with the ltc2410 ltc2420 20-bit, no latency ds adc in so-8 1.2ppm noise, 8ppm inl, pin compatible with ltc2400 ltc2424/ltc2428 4-/8-channel, 20-bit, no latency ds adc 1.2ppm noise, 8ppm inl, pin compatible with ltc2404/ltc2408 ltc2430 20-bit, fully differential, no latency ds adc in ssop-16 0.16ppm noise, 2ppm inl, 10ppm total unadjusted error, 200 m a ltc2431 24-bit, fully differential, no latency ds adc in ms10 0.29ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com typical applicatio u figure 37 shows the block diagram of a demo circuit (contact ltc for a demonstration) of a multichannel isolated temperature measurement system. this circuit decodes an address to select which ltc2422 receives a 24-bit burst of sck signal. all devices independently convert either the thermal couple output or the thermistor cold junction output. after each conversion, the devices enter their sleep state and wait for the sck signal before clocking out data and beginning the next conversion. v cc fs set ch1 sdo sck ch0 zs set ltc2422 a y d1 re r0 ltc1535 v cc fs set ch1 sdo sck ch0 2500v zs set ltc2422 a y d1 re r0 ltc1535 v cc fs set ch1 sdo sck 24212 f37 ch0 zs set ltc2422 a y d1 hc138 hc595 address latch re r0 ltc1535 see figure 34 for the complete circuit hc138 sck sd0 d in (address or counter) + figure 37. mulitchannel isolated temperature measurement system |
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